1. Technical Field
The present invention relates to a semiconductor integrated circuit and a control method thereof, and in particular, to a semiconductor integrated circuit including a delay line of a delay locked loop and a method of controlling a delay time.
2. Related Art
In general, delay lines of a delay locked loop are connected in series and a plurality of delay units having the same delay time are provided.
The delay lines are connected to a delay line control circuit that adjusts the delay time.
As shown in FIG. 1, the delay lines are connected to a delay line control circuit. The delay line control circuit includes a plurality of shift registers 21 to 24, and a plurality of NAND gates ND1 to ND5 having first inputs, to which a clock signal CLK is input, and second inputs to which the outputs of the plurality of shift registers 21 to 24 are correspondingly input.
According to the structure of FIG. 1, if a high signal is output from one of the plurality of shift registers 21 to 24, for example, the shift register 23, the NAND gate ND3 delays and outputs the clock signal by the delay time (hereinafter, referred to as td) defined by the delay unit 13.
If a high signal is output from the shift register 21, the NAND gate ND1 delays and outputs the clock signal by a predetermined time (i.e., 3td) by the delay units 11, 12, and 13.
As shown in FIG. 2, the delay unit 11 according to the related art has two NAND gates. Alternatively, though not shown, the delay unit 11 may have two NOR gates or two inverters. The delay units 12 and 13 have the same structure as the delay unit 11, and thus the descriptions thereof will be omitted.
The NAND gates constituting the delay unit 11 of FIG. 2 are supplied with operating voltages VDD and VSS upon operation. The operating voltages are likely to change for various reasons, such as element characteristics, a change in external environment, and the like.
As the levels of the operating voltages change, the delay time changes. A drop in the operating voltage causes an increase in the delay time td, and a rise in the operating voltage causes a decrease in the delay time td. Further, a change in operating temperature may have an effect on the delay time td.
As the number of delay units constituting the delay line increases, the total delay time of the delay line changes considerably.
The delay time of the delay line in the delay locked loop changes according to the operating environment. A change in operating voltage or operating temperature may cause deterioration of the operating performance of the delay locked loop. In particular, when the delay time of the delay line changes considerably, an error in the operation of a semiconductor integrated circuit to which the delay lock loop is applied, for example, an internal clock becoming out of synchronization with an external clock, may occur.